1. Field of the Invention
Embodiments of the present invention relate to an analog to digital converter and, more particularly, to a multi-gigabit analog to digital converter.
2. Description of Related Art
Data can be transmitted wirelessly using digital modulation. Typically, a receiver receives a wireless signal, which is ultimately digitized using sampling, and then fed to a digital signal processor. Specifically, as illustrated in FIG. 1, the wireless signal is received by an antenna 105, down converted and then sampled by a high resolution analog-to-digital converter (A/D) 110, and finally processed by the digital signal processor (DSP) 115.
Transmitting digital signals is efficient for data at slow speeds. For instance, transmitting using digital modulation and demodulation is preferred for data being transmitted wirelessly at less than 50 megabits per second (Mbps). When it is desired to transmit at higher speeds, i.e., higher than 50 Mbps, digital demodulation is conventionally undesired, as there are many problems. For instance, because there is a need for both a high-resolution, high-speed A/D and a DSP with digital demodulation, the receiver is expensive, high-power consuming, and requires an undesirable large footprint.
Due to the high potential in terms of multi-gigabit wireless transmission using 57-64 GHz unlicensed frequency band (e.g., 59-64 GHz worldwide) for high-speed data transfer between storage devices, point-to-point video, HDTV, and wireless personal area networking (WPAN) applications, it is desirable to either switch to either use analog techniques or develop a high-resolution, high-speed A/D.
Generally, a very high speed A/D is required to sample the baseband signal, and conventionally there is not an available solution. Further, in the case of multi-gigabit signal, implementation of A/D exhibiting sampling rate more than one Giga-sample-per-second (Gsps) results in undesired high power consumption.
High speed A/Ds require high performing: comparators, sample-and-hold circuits, and encoder circuits. Recently, threshold inverting comparators have been investigated as a potential promising solution for ultra-low power and high-speed operation. Unfortunately, such a solution requires new architecture for sample-and-hold circuits and encoder circuits to maintain intrinsic advantages.
What is needed, therefore, is an improved A/D to provide a compact, robust and power-efficient solution. It is to such a method, device, and system that the present invention is primarily directed.